SD 4.0 (UHS-II) achieves a peak interface speed of 3.12 Gbps. Arasan’s UHS-II PHY is compliant with the specification of UHS-II and is an extremely area and power efficient implementation. This ...

Sheffield, UK – 20 May 2025. SureCore, the leading memory specialist, has announced the expansion of its sureFIT design service to include AI applications, using its memory design expertise to help AI ...

COMPUTEX - May 19, 2025 — NVIDIA today unveiled NVIDIA NVLink Fusion™ — new silicon that lets industries build semi-custom AI infrastructure with the vast ecosystem of partners building with NVIDIA ...

EuroHPC is to issue call next month for RISC-V chiplet projects in January with €270m of backing. A Framework Partnership Agreement (FPA) aims to set up a long term partnership between the EuroHPC ...

The Gigabit Ethernet MAC Module (GEM_GXL) is compatible with the IEEE 802.3 Ethernet Standard and supports 10/100/1000M triple speed operation. It supports MII, GMII, RGMII and TBI interfaces to an ...

The UHT-H264E-IDR core from Alma Technologies is a scalable ultra-high throughput H.264 Intra encoder. It is designed to enable 4K UHD resolutions in ...

Analog Bits Programmable SERDES provides a Physical Media Attachment (PMA) Layer capable of signaling at multiple data rates and supports multi-protocol market needs including a wide range of ac- ...

The MIPI D-PHY/C-PHY Combo IP supports data rates of up to 4.5Gbps for D-PHY and 2.5Gsps for C-PHY. It operates in High-Speed (HS), Low-Power (LP), and Escape modes, where High-Speed mode provides ...

Beaverton, OR, USA – September 25, 2017 – USB Implementers Forum (USB-IF), the support organization for the advancement and adoption of USB technology, today announced the publication of the USB 3.2 ...

The Xilinx® LogiCORE™ 32G Fibre Channel (32GFC) RS-FEC IP core implements the Reed-Solomon Forward Error Correction (RS-FEC) sublayer as described in the INCITS ...

The IPrium-CCSDS-SCCC-Modulator-Encoder IP Core implements the CCSDS modulation standard 131.2-B. The IP Core is a complete digital QPSK, 8-PSK, 16-APSK, 32-APSK and 64-APSK modulator with an ...

ASICFPGA Advanced 2D+3D Noise Reduction Core: Noise reduction is a key issue in any camera system to improve the visual appearance of the images. As the light level decreases, the noise level ...