English
全部
搜索
图片
视频
短视频
地图
资讯
更多
购物
航班
旅游
笔记本
报告不当内容
请选择下列任一选项。
无关
低俗内容
成人
儿童性侵犯
Verilog Simulation
Verilog
in Python
Iverilog in Vscode
GitHub SystemVerilog
Using Pyverilog
SystemVerilog Test Bench Tutorial
How to Use Eda Playground
Python-
based RTL Verification
Eda Playground Login
Verilog
Monitor in ModelSim
Tenstorrent Risc vCPU
How to Run Verilog
TB in Vscode
VHDL Test Bench for Xadc Tutorial
Python
Cocotb and ModelSim
Verilog
Project
Veril
Vivado HDL Wrapper
Moving Square in
Verilog
Generating Waveform in SystemVerilog
Python
Cocotb
Clock Generation in SV
How to Use Verilator
Python
FPGA
Cocotb Axi
时长
全部
短(小于 5 分钟)
中(5-20 分钟)
长(大于 20 分钟)
日期
全部
过去 24 小时
过去一周
过去一个月
去年
清晰度
全部
低于 360p
360p 或更高
480p 或更高
720p 或更高
1080p 或更高
源
全部
Dailymotion
Vimeo
Metacafe
Hulu
VEVO
Myspace
MTV
CBS
Fox
CNN
MSN
价格
全部
免费
付费
清除筛选条件
安全搜索:
中等
严格
中等(默认)
关闭
筛选器
Verilog Simulation
Verilog
in Python
Iverilog in Vscode
GitHub SystemVerilog
Using Pyverilog
SystemVerilog Test Bench Tutorial
How to Use Eda Playground
Python-
based RTL Verification
Eda Playground Login
Verilog
Monitor in ModelSim
Tenstorrent Risc vCPU
How to Run Verilog
TB in Vscode
VHDL Test Bench for Xadc Tutorial
Python
Cocotb and ModelSim
Verilog
Project
Veril
Vivado HDL Wrapper
Moving Square in
Verilog
Generating Waveform in SystemVerilog
Python
Cocotb
Clock Generation in SV
How to Use Verilator
Python
FPGA
Cocotb Axi
1:07
Digital Versus Analog: Inverter Modeling, Unpacked #vlsi #coding #asicdesign
已浏览 623 次
4 周前
YouTube
Cadence Design Systems
0:23
Building a Full Adder the Smart Way 🧠⚡ | Verilog Design Using Half Adders (Simulation + RTL)
已浏览 624 次
4 个月之前
YouTube
Sly Fox electronics
2:41
conditional statements in verilog | if else & case
已浏览 183 次
5 个月之前
YouTube
Chip Logic Studio
1:03
Synthesizable vs Non Synthesizable Verilog #cadence #chipdesign
已浏览 1930 次
2 个月之前
YouTube
Cadence Design Systems
2:52
Verilog Counter Code with Testbench & Simulation | Complete Tutorial for Beginners
已浏览 688 次
3 个月之前
YouTube
Chip Logic Studio
0:59
Verilog lecture 1 || Verilog HDL by Samir palnitkar || || How to learn Verilog #verilog
已浏览 794 次
3 个月之前
YouTube
Aditya Singh
0:49
🚀 FREE One-Day VLSI Workshop- SOC Design Using Verilog | Best VLSI Offline Training & Online Courses
已浏览 541 次
1 个月前
YouTube
VLSI FOR ALL
1:04
What is Synthesis? #cadence #computerengineering #chipdesign
已浏览 915 次
1 个月前
YouTube
Cadence Design Systems
2:52
Encoder in Verilog HDL with Testbench | RTL Simulation for VLSI Interviews
已浏览 77 次
4 个月之前
YouTube
Chip Logic Studio
2:57
2-bit Adder to 4-bit Adder in Verilog | Structural Modeling + Testbench + Simulation
已浏览 1522 次
3 个月之前
YouTube
Chip Logic Studio
1:24
Difference between Data types of Verilog and SystemVerilog #cadence #chipdesign
已浏览 1055 次
2 个月之前
YouTube
Cadence Design Systems
1:10
Difference Between Assignment and Contribution Operator in 60 seconds
已浏览 261 次
1 个月前
YouTube
Cadence Design Systems
6:39
Học Ngành Vi Mạch Bán Dẫn: Cơ Hội và Thách Thức
已浏览 10.7万 次
10 个月之前
TikTok
thayquyethuongnghiep
0:15
FPGA para aplicaciones espaciales
已浏览 1.8万 次
2025年6月29日
TikTok
capsula.electronica
0:10
Stratosky FPGA - Rumbo a México
已浏览 3269 次
5 个月之前
TikTok
capsula.electronica
0:49
You NEED a complete and up to date LinkedIn profile in 2026. LinkedIn is essentially a search engine for recruiters—if your profile doesn’t have the right keywords, you won’t be found or considered for interviews. To fix this, you need to: 🔑 Target Keywords: Add technical skills like (ex. Python, Verilog, or UVM) to your headline, about section, and experience. 🖼️ Build a Portfolio: Don’t just list skills—post photos of your hardware builds or screen recordings of your code. 📄 Pin Your Resume
已浏览 3966 次
6 个月之前
TikTok
engcalebj28
0:12
FPGA Project: 7 Segment LED Display with Verilog
已浏览 5450 次
10 个月之前
TikTok
furt_tech
0:35
FPGAs Peruanas: Prototipo Oficial y Entrenamiento
已浏览 1.1万 次
2024年11月12日
TikTok
capsula.electronica
Servomotor con FPGA NANO 1k: Proyecto Mecatrónico
已浏览 6245 次
11 个月之前
TikTok
fpgaedudesign
0:16
Cansados pero felices ,salieron 50 nuevas unidades de placas FPGAs StratoSky para Latam ,gracias Dios por la bendición #verilog #fpgas #systemverilog #Stratosky #vhdl
已浏览 1357 次
4 个月之前
TikTok
capsula.electronica
展开
更多类似内容
反馈