English
全部
搜索
图片
视频
短视频
地图
资讯
更多
购物
航班
旅游
笔记本
报告不当内容
请选择下列任一选项。
无关
低俗内容
成人
儿童性侵犯
Verilog
Coding Tutorial
Verilog
Basics
VHDL
Programming
NPTEL Verilog
Lectures
SystemVerilog
Tutorials
Verilog
Training
Verilog
HDL Tutorial
USB Verilog
Example
Verilog
Inverter
How to Start
Verilog
Verilog
Introduction
Clock Divider
Verilog
Verilog
Course
Verilog
Code
时长
全部
短(小于 5 分钟)
中(5-20 分钟)
长(大于 20 分钟)
日期
全部
过去 24 小时
过去一周
过去一个月
去年
清晰度
全部
低于 360p
360p 或更高
480p 或更高
720p 或更高
1080p 或更高
源
全部
Dailymotion
Vimeo
Metacafe
Hulu
VEVO
Myspace
MTV
CBS
Fox
CNN
MSN
价格
全部
免费
付费
清除筛选条件
安全搜索:
中等
严格
中等(默认)
关闭
筛选器
Verilog
Coding Tutorial
Verilog
Basics
VHDL
Programming
NPTEL Verilog
Lectures
SystemVerilog
Tutorials
Verilog
Training
Verilog
HDL Tutorial
USB Verilog
Example
Verilog
Inverter
How to Start
Verilog
Verilog
Introduction
Clock Divider
Verilog
Verilog
Course
Verilog
Code
2:52
YouTube
Chip Logic Studio
Verilog Counter Code with Testbench & Simulation | Complete Tutorial for Beginners
Verilog Counter Code with Testbench & Simulation | Complete Tutorial for Beginners Welcome to Chip Logic Studio (CLS) 🚀 In this video, we learn how to design a Counter in Verilog HDL, write a complete Testbench, and perform RTL Simulation step by step. This tutorial is perfect for beginners in VLSI, Digital Design, and Verilog Programming ...
已浏览 688 次
3 个月之前
观看完整视频
短视频
0:23
已浏览 61 次
Building a Full Adder the Smart Way 🧠⚡ | Verilog Design Using Half Adders
Sly Fox electronics
1:03
已浏览 1930 次
Synthesizable vs Non Synthesizable Verilog #cadence #chipdesign
Cadence Design Systems
Verilog Tutorial
2:57
2-bit Adder to 4-bit Adder in Verilog | Structural Modeling + Testbench + Simulation
YouTube
Chip Logic Studio
已浏览 1522 次
3 个月之前
2:57
Verilog Counter Code with Testbench & Simulation | Complete Tutorial for Beginners
YouTube
Chip Logic Studio
已浏览 88 次
3 个月之前
1:53
Verilog Course Day 10 | Master Functions and Tasks
YouTube
Chip Logic Studio
已浏览 201 次
6 个月之前
热门视频
0:59
Verilog lecture 1 || Verilog HDL by Samir palnitkar || || How to learn Verilog #verilog
YouTube
Aditya Singh
已浏览 794 次
3 个月之前
1:07
Digital Versus Analog: Inverter Modeling, Unpacked #vlsi #coding #asicdesign
YouTube
Cadence Design Systems
已浏览 623 次
1 个月前
2:41
conditional statements in verilog | if else & case
YouTube
Chip Logic Studio
已浏览 183 次
5 个月之前
Verilog Examples
1:10
Difference Between Assignment and Contribution Operator in 60 seconds
YouTube
Cadence Design Systems
已浏览 261 次
1 个月前
2:32
Verilog Day 11: : Arrays in Verilog
YouTube
Chip Logic Studio
已浏览 152 次
5 个月之前
2:56
Verilog Day 11: : Arrays in Verilog
YouTube
Chip Logic Studio
已浏览 75 次
5 个月之前
0:59
Verilog lecture 1 || Verilog HDL by Samir palnitkar || || How to learn Verilog #verilog
已浏览 794 次
3 个月之前
YouTube
Aditya Singh
1:07
Digital Versus Analog: Inverter Modeling, Unpacked #vlsi #coding #asicdesign
已浏览 623 次
1 个月前
YouTube
Cadence Design Systems
2:41
conditional statements in verilog | if else & case
已浏览 183 次
5 个月之前
YouTube
Chip Logic Studio
0:23
Building a Full Adder the Smart Way 🧠⚡ | Verilog Design Using Half Adders (Simulation + RTL) [short]
已浏览 61 次
1 个月前
YouTube
Sly Fox electronics
1:03
Synthesizable vs Non Synthesizable Verilog #cadence #chipdesign
已浏览 1930 次
2 个月之前
YouTube
Cadence Design Systems
2:57
2-bit Adder to 4-bit Adder in Verilog | Structural Modeling + Testbench + Simulation
已浏览 1522 次
3 个月之前
YouTube
Chip Logic Studio
2:57
Verilog Counter Code with Testbench & Simulation | Complete Tutorial for Beginners
已浏览 88 次
3 个月之前
YouTube
Chip Logic Studio
1:53
Verilog Course Day 10 | Master Functions and Tasks
已浏览 201 次
6 个月之前
YouTube
Chip Logic Studio
1:10
Difference Between Assignment and Contribution Operator in 60 seconds
已浏览 261 次
1 个月前
YouTube
Cadence Design Systems
2:32
Verilog Day 11: : Arrays in Verilog
已浏览 152 次
5 个月之前
YouTube
Chip Logic Studio
2:56
Verilog Day 11: : Arrays in Verilog
已浏览 75 次
5 个月之前
YouTube
Chip Logic Studio
2:21
Verilog Day 1: Introduction and Data Types Explained from Scratch
已浏览 258 次
8 个月之前
YouTube
Chip Logic Studio
2:59
Verilog Day 1: Introduction and Data Types Explained from Scratch
已浏览 98 次
8 个月之前
YouTube
Chip Logic Studio
2:52
Encoder in Verilog HDL with Testbench | RTL Simulation for VLSI Interviews
已浏览 34 次
4 个月之前
YouTube
Chip Logic Studio
2:57
Verilog Counter Code with Testbench & Simulation | Complete Tutorial for Beginners
已浏览 170 次
3 个月之前
YouTube
Chip Logic Studio
0:23
Building a Full Adder the Smart Way 🧠⚡ | Verilog Design Using Half Adders (Simulation + RTL)
已浏览 624 次
4 个月之前
YouTube
Sly Fox electronics
2:52
Decoder in Verilog HDL with Testbench | RTL Simulation for VLSI Interviews
已浏览 59 次
4 个月之前
YouTube
Chip Logic Studio
2:29
Verilog Day 7: System Tasks Explained
已浏览 45 次
7 个月之前
YouTube
Chip Logic Studio
0:49
🚀 FREE One-Day VLSI Workshop- SOC Design Using Verilog | Best VLSI Offline Training & Online Courses
已浏览 541 次
1 个月前
YouTube
VLSI FOR ALL
展开
更多类似内容
反馈